library verilog;
use verilog.vl_types.all;
entity present_encryptor_top is
    port(
        data_o          : out    vl_logic_vector(63 downto 0);
        data_i          : in     vl_logic_vector(79 downto 0);
        data_load       : in     vl_logic;
        key_load        : in     vl_logic;
        clk             : in     vl_logic;
        encry_ok        : out    vl_logic
    );
end present_encryptor_top;
